open-earable-exg-factsheet

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open-earable-exg-factsheet [2026/06/11 16:28] – created fabricioopen-earable-exg-factsheet [2026/06/11 16:31] (current) – [Firmware] fabricio
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 ====== External microSD reader — wiring guide (OpenEarable ExG) ====== ====== External microSD reader — wiring guide (OpenEarable ExG) ======
  
-  The internal microSD slot shares its chip-select with the AD7124 ExG ADC +The internal microSD slot shares its chip-select with the AD7124 ExG ADC 
-  (board defect, see hardware notes): the two are mutually exclusive per +(board defect, see hardware notes): the two are mutually exclusive per 
-  power-cycle. This guide adds an **external SD reader on a separate SPI bus** +power-cycle. This guide adds an **external SD reader on a separate SPI bus** 
-  using the two accessory connectors, so **ExG sampling and SD logging can run +using the two accessory connectors, so **ExG sampling and SD logging can run 
-  simultaneously**.+simultaneously**.
  
-  ===== What you need =====+===== What you need =====
  
-    * Bare **3.3 V microSD breakout** (socket only — //no// 5 V level shifters or regulators; Arduino-style 5 V shields are unsuitable) +  * Bare **3.3 V microSD breakout** (socket only — //no// 5 V level shifters or regulators; Arduino-style 5 V shields are unsuitable) 
-    * **JST SH 4-pin cable** for J2 — any Qwiic / STEMMA-QT cable fits mechanically (housing SHR-04V-S-B) +  * **JST SH 4-pin cable** for J2 — any Qwiic / STEMMA-QT cable fits mechanically (housing SHR-04V-S-B) 
-    * **JST SH 8-pin cable** for P1 (housing SHR-08V-S-B), only 3–4 wires used +  * **JST SH 8-pin cable** for P1 (housing SHR-08V-S-B), only 3–4 wires used 
-    * microSD card, FAT32 formatted+  * microSD card, FAT32 formatted
  
-  :!: **Pin order on J2 is NOT Qwiic order.** Qwiic cables are wired GND, 3V3, SDA, SCL — J2 is SCL, GND, 3V3, SDA. Always go by **pin position**, never +:!: **Pin order on J2 is NOT Qwiic order.** Qwiic cables are wired GND, 3V3, SDA, SCL — J2 is SCL, GND, 3V3, SDA. Always go by **pin position**, never by wire color.
-  by wire color.+
  
-  ===== Wiring table =====+===== Wiring table =====
  
-  ^ SD breakout signal ^ Connector ^ Part (JST) ^ Conn. pin ^ Board net ^ NINA module pin ^ nRF GPIO ^ +^ SD breakout signal ^ Connector ^ Part (JST) ^ Conn. pin ^ Board net ^ NINA module pin ^ nRF GPIO ^ 
-  | SCK  | P1 | SM08B-SRSS-TB | P1.8 | ''PDMCLK'' | 42 | P0.26 | +| SCK  | P1 | SM08B-SRSS-TB | P1.8 | ''PDMCLK'' | 42 | P0.26 | 
-  | MOSI | P1 | SM08B-SRSS-TB | P1.7 | ''PDMDIN'' | 7  | P0.25 | +| MOSI | P1 | SM08B-SRSS-TB | P1.7 | ''PDMDIN'' | 7  | P0.25 | 
-  | MISO | J2 | SM04B-SRSS-TB | J2.4 | ''SDA''    | 20 | P0.31 | +| MISO | J2 | SM04B-SRSS-TB | J2.4 | ''SDA''    | 20 | P0.31 | 
-  | CS   | J2 | SM04B-SRSS-TB | J2.1 | ''SCL''    | 18 | P0.02 | +| CS   | J2 | SM04B-SRSS-TB | J2.1 | ''SCL''    | 18 | P0.02 | 
-  | VDD (3.3 V) | P1 //or// J2 | | P1.6 or J2.3 | ''+3V3'' | — | — | +| VDD (3.3 V) | P1 //or// J2 | | P1.6 or J2.3 | ''+3V3'' | — | — | 
-  | GND  | P1 //or// J2 | | P1.3 or J2.2 | GND | — | — |+| GND  | P1 //or// J2 | | P1.3 or J2.2 | GND | — | — |
  
-  Pin 1 on both connectors is marked on the board silk; JST SH connectors are +Pin 1 on both connectors is marked on the board silk; JST SH connectors are 
-  keyed, so the housing only fits one way.+keyed, so the housing only fits one way.
  
-  ===== Step by step =====+===== Step by step =====
  
-    - **Power off** the board (unplug USB; the 3V3 rail must be dead while wiring). +  - **Power off** the board (unplug USB; the 3V3 rail must be dead while wiring). 
-    - **Remove any card from the internal slot** — an inserted card sits electrically on the ADC's SPI bus and must stay out. +  - **Remove any card from the internal slot** — an inserted card sits electrically on the ADC's SPI bus and must stay out. 
-    - Plug the 4-pin SH cable into **J2**, the 8-pin SH cable into **P1**. +  - Plug the 4-pin SH cable into **J2**, the 8-pin SH cable into **P1**. 
-    - Connect to the breakout: +  - Connect to the breakout: 
-      * J2 pin 1 (''SCL'', P0.02) → **CS** +    * J2 pin 1 (''SCL'', P0.02) → **CS** 
-      * J2 pin 4 (''SDA'', P0.31) → **MISO** +    * J2 pin 4 (''SDA'', P0.31) → **MISO** 
-      * P1 pin 7 (''PDMDIN'', P0.25) → **MOSI** +    * P1 pin 7 (''PDMDIN'', P0.25) → **MOSI** 
-      * P1 pin 8 (''PDMCLK'', P0.26) → **SCK** +    * P1 pin 8 (''PDMCLK'', P0.26) → **SCK** 
-      * P1 pin 6 //or// J2 pin 3 (''+3V3'') → **VDD** +    * P1 pin 6 //or// J2 pin 3 (''+3V3'') → **VDD** 
-      * P1 pin 3 //or// J2 pin 2 (GND) → **GND** +    * P1 pin 3 //or// J2 pin 2 (GND) → **GND** 
-    - Insulate/trim the unused P1 wires (pins 1, 2, 4, 5 — speaker outputs and the IMU's I²C bus; **do not** let them touch anything). +  - Insulate/trim the unused P1 wires (pins 1, 2, 4, 5 — speaker outputs and the IMU's I²C bus; **do not** let them touch anything). 
-    - Keep the cable run short (< 10 cm) — the bus runs at 8 MHz unshielded. +  - Keep the cable run short (< 10 cm) — the bus runs at 8 MHz unshielded. 
-    - Insert the card into the **external** breakout, power the board back up.+  - Insert the card into the **external** breakout, power the board back up.
  
-  ===== Why these pins =====+===== Why these pins =====
  
-    * P0.25 / P0.26 were reserved for a PDM microphone that was never fitted — completely free. +  * P0.25 / P0.26 were reserved for a PDM microphone that was never fitted — completely free. 
-    * P0.02 / P0.31 are the external-I²C header pins, unused by any on-board device. Their I²C pull-ups (R2, R15) are a bonus: the pull-up on **CS** keeps +  * P0.02 / P0.31 are the external-I²C header pins, unused by any on-board device. Their I²C pull-ups (R2, R15) are a bonus: the pull-up on **CS** keeps the card deselected during boot/reset, and the pull-up on **MISO** gives a clean idle-high line — the same safeguards the internal slot lacks. 
-  the card deselected during boot/reset, and the pull-up on **MISO** gives a clean idle-high line — the same safeguards the internal slot lacks. +  * The IMU's bus (P1 pins 4/5) and the speaker outputs (P1 pins 1/2) remain untouched and available.
-    * The IMU's bus (P1 pins 4/5) and the speaker outputs (P1 pins 1/2) remain untouched and available.+
  
-  ===== Limitations & cautions =====+===== Limitations & cautions =====
  
-    * **3.3 V logic only** — never feed the breakout from 5 V. +  * **3.3 V logic only** — never feed the breakout from 5 V. 
-    * SD write bursts draw 50–100 mA: fine for the regulator, but noticeable against the 90 mAh battery; budget accordingly. +  * SD write bursts draw 50–100 mA: fine for the regulator, but noticeable against the 90 mAh battery; budget accordingly. 
-    * If BLE range/throughput degrades during heavy SD writes, halve the SPI clock to 4 MHz and re-test (some nRF52840 pins near the radio are recommended +  * If BLE range/throughput degrades during heavy SD writes, halve the SPI clock to 4 MHz and re-test (some nRF52840 pins near the radio are recommended low-frequency I/O). 
-  low-frequency I/O). +  * The internal slot remains unusable for data while ExG is active — leave it empty permanently.
-    * The internal slot remains unusable for data while ExG is active — leave it empty permanently.+
  
-  ===== Firmware =====+===== Firmware =====
  
-  The Zephyr side needs a second SPI controller (SPIM2) mapped to these four +The Zephyr side needs a second SPI controller (SPIM2) mapped to these four  pins with an SD-over-SPI slot on it — the same stack already proven on the 
-  pins with an SD-over-SPI slot on it — the same stack already proven on the +internal slot (''bringup/test_sd_cs17''). See the board devicetree and 
-  internal slot (''bringup/test_sd_cs17''). See the board devicetree and +''HARDWARE.md'' in the firmware repo for the authoritative pin map.
-  ''HARDWARE.md'' in the firmware repo for the authoritative pin map.+
  
-  One thing to double-check against your physical board before crimping: the pin-1 orientation of P1 and J2 (silk dot/triangle) — the netlist gives pin +One thing to double-check against your physical board before crimping: the pin-1 orientation of P1 and J2 (silk dot/triangle) — the netlist gives pin 
-  numbers but not how the footprint is rotated on your board revision. A multimeter continuity check from J2.2/P1.3 to any GND point (e.g., USB shield) +numbers but not how the footprint is rotated on your board revision. A multimeter continuity check from J2.2/P1.3 to any GND point (e.g., USB shield) 
-  confirms you've got the orientation right before anything gets power.+confirms you've got the orientation right before anything gets power.
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  • Last modified: 2026/06/11 16:28
  • by fabricio